1. Field of the Invention
The present disclosure relates to a tin-based electroplating solution that is used to form solder bumps in a flip-chip packaging process.
2. Description of the Related Art
With the advent of small, slim, high-performance electronics, there has been an increasing demand for fast operation and improved electrode density of essential devices, such as memories. Under such circumstances, flip-chip packaging techniques are rapidly extended and applied to the fabrication of electronic devices. Conventional wire bonding processes involve connecting chips to boards with fine wires. Tape automated bonding (TAB) processes involves arranging chips on flexible tapes. However, these conventional processes have limitations in achieving reduced system size or improved electrical performance. In flip-chip packaging processes, solder bumps are formed on a pad of integrated circuit chips and are directly bonded to a circuit board by heating. That is, flip-chip packaging processes are area array packaging processes that utilize the entire area of chips, unlike wire bonding or TAB processes using only the edges of chips. Therefore, flip-chip packaging processes enable the formation of a significantly increased number of input/output terminals per unit area and are thus suitable for fine pitch applications. In addition, flip-chip packaging processes use solder bumps whose length is shorter than bonding wires, ensuring excellent electrical properties. Due to these advantages, flip-chip packaging processes can minimize the size of packages, thus being suitable for the manufacture of lightweight, thin, compact, high-performance, and fast operating electronic products. In addition, flip-chip packaging processes can provide a solution to noise problems. Such techniques are extendable and applicable to the display, semiconductor, and other relevant industries, including CPU and memory industries.
Such flip chip packages take various forms, but most of them use solder bumps composed of copper (or copper/nickel) pillars and tin alloy bumps on a copper-based under bump metallurgy (UBM) layer. Many problems need to be solved in the development of processes for the formation of alloy-based solder bumps. For example, there are problems associated with defectiveness, yield, and quality of products, such as height variations of within die (WID) and within wafer (WIW) bumps, the formation of empty space inside bumps, and the occurrence of cracks in intermetallic compound layers.